The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of a variety of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from repeated reductions in minimum feature size, which allows more components to be integrated into a given area. As the demand for even smaller electronic devices has grown recently, there has grown a need for smaller and more creative packaging techniques of semiconductor dies.
As semiconductor technologies evolve, chip-scale or chip-size packaging based semiconductor devices have emerged as an effective alternative to further reduce the physical size of a semiconductor chip. In a chip-scale packaging based semiconductor device, the packaging is generated on the die with contacts provided by a variety of bumps. Much higher density can be achieved by employing chip-scale packaging based semiconductor devices. Furthermore, chip-scale packaging based semiconductor devices can achieve smaller form factors, cost-effectiveness, increased performance and lower power consumption.
A chip-scale packaging based semiconductor device may comprise a plurality of solder balls formed on a plurality of under bump metal (UBM) openings of a semiconductor die. Due to the mismatch between different materials in a chip-scale package, greater stress may be generated on the corners or the edges of the chip-scale package. As a result, the corners or the edges of the chip-scale package are prone to failures. Possible failures comprise extreme low k (ELK) material layer cracks, solder bump cracks and the like. The stress can be reduced by using an adequate enclosure underneath the under bump metal structures.
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the various embodiments and are not necessarily drawn to scale.